• QR Decomposition (Orthogonal-Triangular Matrix Factorization)
• LU Decomposition (Factors a matrix into two triangular matrices)
• ICA (Blind source separation via statistical independence)
• GDDR7 (Ultra-high-speed data transfer for graphics processors)
• GDDR (Dedicated high-speed memory for graphics processors)
• RDNA4 (Chiplet architecture with enhanced compute units)
• Turbo Boost (Automatic core clock frequency increase)
• L1D (Ultra-fast data buffering for the core)
• L1I (Level 1 instruction cache)
• LLC (Shared cache memory for all processor cores)
• MEC (Parallel task execution in memory)
• MOB (Buffer that orders memory operations)
• WCB (Merging write operations in memory)
• PFLOPS (Measuring the computational power of supercomputers)
• INT8 (Quantization of neural network weights and activations)
• FP8 (Compact representation of numbers for fast computations)
• SoC (Integration of all computer components on a single chip)
• APU (Hybrid processor with shared memory)
• KV Cache (Caching previous attention keys and values)
• FLOP (Arithmetic operation on floating-point numbers)
• TPU (Specialized accelerator for tensor multiplication operations)
• PCA (Dimensionality reduction with variance preservation)
• SVD (Matrix factorization into three components)
• NPU (Specialized processor for parallel tensor computations)
• OLED (Converting electricity into light with organic pixels)
• DisplayPort (High-speed video and audio transmission)
• AV1 (Video codec for streaming)
• HEVC (Effective video compression with minimal losses)
• AVC (Video compression with motion prediction)
• CUDA (Parallel computing on the graphics processing unit)
• VRR (Syncing display refresh rate with frames)
• FreeSync (Dynamic synchronization of monitor and graphics card frames)
• G-Sync (Dynamic synchronization of monitor and GPU frames)
• FSR (Spatial scaling with detail reconstruction)
• DLSS (Smart scaling and smoothing with a neural network)
• RT Core (Hardware accelerated ray tracing)
• Tensor Core (Hardware matrix multiplication with accumulation)
• CUDA Core (Performing parallel floating point computations)
• VRAM (High-speed buffer for graphical data)
• TDP (Project processor heat dissipation limit)
• AES-NI (Hardware acceleration of symmetric AES encryption)
• AVX-512 (Processing 16 numbers per instruction)
• AVX2 (Simultaneous processing of eight 32-bit integers)
• AVX (SIMD data processing with 256/512-bit registers)
• SSE (Simultaneous processing of multiple data with a single instruction)
• MMX (Single-cycle processing of packed integer data)
• TLB (Translation Lookaside Buffer)
• SMT (Hardware emulation of two logical processors)
• MMU (Translation of virtual addresses to physical addresses)
• IPC (Instructions per cycle)
• TFLOPS (Computational performance meter)
• TOPS (Measuring peak performance of AI accelerators)
• FP16 (Compact representation of Floating-Point numbers)
• BF16 (Floating-point number format for machine learning)
• TF32 (Hybrid format for accelerating tensor computations)
• Peer2Peer (Direct memory access between GPUs)
• XGMI (AMD high-speed coherent Inter-Die bus)
• XeSS (Intelligent upscaling with frame reconstruction)
• FSR4 (Next-generation neural network scaling)
• LFB (Cache Line Fill Buffer)
• LSU (Execution of load and store operations)
• IFU (Instruction Fetch and Decode)
• IDU (Transforming instructions into control signals)
• ARF (Fast architectural register storage file)
• Eigenvector (A vector that preserves direction under transformation)
• APIC (Interrupt Routing and Prioritization in multiprocessor systems)
• NVDIMM (Preservation of RAM data during power loss)
• PRF (Storage of renamed microarchitectural operands)
• RAT (Eliminating false dependencies between registers)
• RS (Buffering and dynamic instruction scheduling)
• Eigenvalue (Scaling your own vector without rotation)
• ROB (Reorder buffer for out-of-order operations)
• RSB (Return address prediction buffer)
• Kronecker Product (Building a block matrix through scaling)
• Hadamard Product (Element-wise multiplication of matrices of the same size)
• BTB (Prediction of the next branch instruction address)
• BPU (Branch prediction for pipeline acceleration)
• AGU (Computing effective memory addresses)
• EU (Execution of machine instructions by the processor)
• CU (Managing the execution of machine instructions of the processor)
• FPU (Hardware acceleration of floating point computations)
• ALU (Performs arithmetic and logical operations)
• ZISC (Hardware nearest match search)
• OISC (Performing computations through a single universal instruction)
• MISC (Executing commands through a single universal instruction code)
• VLIW (Parallel execution of commands without a hardware scheduler)
• RISC (Accelerated execution of simple commands by the processor)
• CISC (Executing complex operations with a single instruction)
• EPIC (Division of responsibility for execution parallelism)
• GEMM (Matrix multiplication using the row times column method)
• Inner Product (Weighted sum of pairwise coordinate products)
• Itanium (Explicit static scheduling of parallel instructions)
• UltraSPARC (64-bit RISC microprocessor architecture with out-of-order execution)
• SPARC (Open standard RISC architecture)
• POWER10 (Multithreaded scaling with hardware AI acceleration)
• PowerPC (RISC architecture with computation optimization)
• MIPS64 (64-bit RISC architecture with fixed instruction length)
• MIPS32 (32-bit RISC architecture with fixed instruction length)
• MIPS (Simplified pipelined RISC architecture without interlocks)
• Dot Product (Summing products of two vectors)